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AD7653 데이터시트(PDF) 15 Page - Analog Devices

부품명 AD7653
상세설명  16-Bit, 6 MSPS, PulSAR Differential ADC
PDF  24 Pages
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제조업체  AD [Analog Devices]
홈페이지  http://www.analog.com
Logo AD - Analog Devices

AD7653 데이터시트(HTML) 15 Page - Analog Devices

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Data Sheet
AD7625
Rev. A | Page 15 of 24
TYPICAL CONNECTION DIAGRAM
1 SEE THE LAYOUT, DECOUPLING, AND GROUNDING SECTION.
2 C
REF IS USUALLY A 10µF CERAMIC CAPACITOR WITH LOW ESR AND ESL.
3 USE PULL-UP OR PULL-DOWN RESISTORS TO CONTROL EN0, EN1 DURING POWER-UP. EN0 AND EN1 INPUTS CAN BE
FIXED IN HARDWARE OR CONTROLLED USING A DIGITAL HOST (EN0 = 0 AND EN1 = 0 IS AN ILLEGAL STATE).
4 OPTION TO USE A CMOS (CNV+) OR LVDS (CNV±) INPUT TO CONTROL CONVERSIONS.
5 TO ENABLE SELF-CLOCKED MODE, TIE DCO+ TO GND USING A PULL-DOWN RESISTOR.
6 CONNECT PIN 19 AND PIN 20 TO VDD1 SUPPLY; ISOLATE FROM PIN 1 USING A FERRITE BEAD SIMILAR TO WURTH 74279266.
7 SEE THE DRIVING THE AD7625 SECTION FOR DETAILS ON AMPLIFIER CONFIGURATIONS.
8 SEE THE VOLTAGE REFERENCE OPTIONS SECTION FOR DETAILS.
AD7625
CREF
10µF1, 2
V+
ADR4348
ADR444
CONVERSION4
CONTROL
CMOS (CNV+ ONLY)
OR
LVDS CNV+ AND CNV–
USING 100Ω
TERMINATION RESISTOR
DIGITAL INTERFACE SIGNALS
DIGITAL HOST
LVDS TRANSMIT AND RECEIVE
VDD1
VDD2
CAP1
REFIN
EN0
EN1
VDD2
24
23
22
21
20
19
18
GND
IN+
IN–
VCM
VDD1
VDD1
VDD2
10nF
100nF
100nF
10µF
ADR2808
VIO
10kΩ3
1
0kΩ
CONTROL FOR
ENABLE
PINS
VIO
(2.5V)
5
1
00Ω
100Ω
PADDLE
CAPACITOR ON OUTPUT
FOR STABILITY
10µF1
100nF
100nF
FERRITE
BEAD6
VDD1
(5V)
VDD2
(2.5V)
VDD1
(5V)
VDD2
(2.5V)
100nF
VDD2
(2.5V)
IN+
IN–
VCM
SEE THE DRIVING
THE AD7625 SECTION7
8
9
10
11
12
13
14
15
16
17
1
00Ω
100Ω
1
2
3
4
5
6
7
32
31
30
29
28
27
26
25
Figure 22. Typical Application Diagram



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