MB40C328VPFV datasheet(11/16 Pages) FUJITSU

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MB40C328V

s TIMING DIAGRAM 3

CLK input-demultiplex output (two-phase) mode

• CLK = 100 MHz (max)

• CLKA = CLKB = “L” (DVSS)

• CKSEL = “L” (AVSS)

•DSEL = “H” (DVDD)

•CE = “L” (AVSS)

•OE = “L” (DVSS)

•VINA input — Sampling at CLK rising

•DA0 to DA7 — Output (after 5 CLK + tpdM2 from Sampling) at CLK rising

•DB0 to DB7 — Output (after 5 CLK + tpdM2 from Sampling) at CLK rising

VIHD

VILD

VOHD

VOLD

VOHD

VOLD

DB0 to DB7

DA0 to DA7

VOHD

VOLD

CLKOA

VOHD

VOLD

CLKOB

VIHD

VILD

tAD

DVDD

− 0.5 V

+ 1 N + 2N + 3 N + 4

+ 5

+ 10

+ 9

+ 8

+ 7

+ 6

tWS+

tWS−

0.5 V

1.5 V

or N

− 10

or N

− 9

or N

− 8

− 7

or N

− 8

− 5

or N

− 6

− 3

or N

− 4

− 1

or N

− 2

0.4 V

DVDD

− 0.4 V

tpdM2(max)

tpdM2(typ)

0.4 V

DVDD

−0.4 V

tpdM2(max)

tpdM2(typ)

tpdM2(min)

0.4 V

DVDD

− 0.4 V

tpdM2O(max)

tpdM2O(typ)

tpdM2O(min)

0.4 V

DVDD

− 0.4 V

tpdM2O(max)

tpdM2O(typ)

tpdM2O(min)

− 10

or N

− 9

− 8

or N

− 7

− 8

or N

− 7

− 6

or N

− 5

− 4

or N

− 3

− 2

1.5 V

tpdM2(min)

+ 1

− 3

− 1

− 2

− 9N − 9

+ 3

+ 2

CLK input

RESET input

VINA input

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