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MB40C328VPFV 데이터시트(PDF) 3 Page - fujitsu semiconductor |
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MB40C328VPFV 데이터시트(HTML) 3 Page - fujitsu semiconductor |
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3 / 16 page ![]() 3 MB40C328V s PIN DESCRIPTION The values in parentheses are standard. Pin No. Symbol Description 3, 9, 13, 45 AVDD Analog power supply (+3.3 V) 16, 43 DVDD Digital power supply (+3.3 V) 27 DVDDI Digital power supply for digital input (+5 V) 4, 7, 12, 44 AVSS Analog power supply ground pin (0 V) 18, 32, 41 DVSS Digital power supply ground pin (0 V) 33 to 40 DA7 to DA0 Digital output pin (Port A) DA7: MSB, DA0: LSB 19 to 26 DB7 to DB0 Digital output pin (Port B) DB7: MSB, DB0: LSB 11 CE Power down at CE input “H” (internal pull-up resistor) 14 OE Digital output (Both Port A, B) and clock output (CLKOA, CLKOB) are high impedance at OE input “H”. 10 CKSEL Mode of operation setting input pin (Refer to s MODE SETTING) 15 DSEL 28 RESET Dividing circuit reset input pin (See s TIMING DIAGRAM 2, 3) 29 CLK Clock input pin (max 100 MHz) 31 CLKA A ch clock input pin (max 50 MHz) 30 CLKB B ch clock input pin (max 50 MHz) 42 CLKOA Clock output pin (See s TIMING DIAGRAM 1 to 4) 17 CLKOB Clock output pin (See s TIMING DIAGRAM 1 to 4) 8VINA Analog input pin Input range is VRT to VRB (0 V to 3.0 V: 2 Vp-p) 2 1 48 VR1 VR2 VR3 Reference 1/4 voltage output pin (Add 0.1 µF for AVSS) Reference 1/2 voltage output pin (Add 0.1 µF for AVSS) Reference 3/4 voltage output pin (Add 0.1 µF for AVSS) 46 VRT Reference voltage input pin on top side 47 VREFT Reference voltage output pin By connecting to VRT, 0.9 × AVDD ( 3 V) is generated. 6VRB Reference voltage input pin on bottom side 5VREFB Reference voltage output pin By connecting to VRB, 0.3 × AVDD ( 1 V) is generated. . . = . . = |
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