MB86604LPFV datasheet(9/56 Pages) FUJITSU

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MB86604L

s BLOCK DESCRIPTION

International Processor (Sequencer)

Performs sequence control between the SCSI bus phases.

Timer

Manages the SCSI time standards.

Also, conducts the following time managements.

• Time until the REQ or ACK signal is asserted for asychronous transfer data

• Time until selection or reselection is retried

•REQ and ACK timeout time during transfers:

Asychronous transfer case

Target:

After the REQ is asserted, the time until the initiator asserts the ACK

Initiator: After the ACK is asserted, the time until the target negates the REQ

Synchronous transfer case

Target:

After the REQ is sent, the time until an ACK signal which makes the offset 0 is received from the

initiator

• SPC Timeout

Manages the SPC timeout indicating the SPC busy time longer than the specified time.

Phase Controller

Controls the various phases executed by SCSI such as arbitration, selection/reselection, data in/out, command,

status, and message in/out.

Transfer Controller

Controls the information (data, command, status, message) transfer phases executed by SCSI.

The following two types of transfer phases are used.

Asychronous transfer: Controls interlock (response confirmation format) between the REQ and ACK signals.

Synchronous transfer: Controls a maximum 32-byte offset value for the data in or data out phase.

The following two modes exist for the data phase.

Program transfer: Uses data register (address 00/01) via the MPU interface

DMA transfer: Uses DREQ and DACK signals via the DMA interface.

The transfer parameter setting values for synchronous transfer (Transfer mode, transfer rate, transfer offset) can be

strobe for individual ID device and are automatically established when the data phase is initiated.

The number of transfer bytes is defined as block length

× number of blocks.

Bus free phase

Arbitration phase

Selection phase

Information transfer

phase

Information transfer phase:

• Command phase

• Data phase

• Status phase

• Message phase

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