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AS5050A 데이터시트(PDF) 14 Page - ams AG |
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AS5050A 데이터시트(HTML) 14 Page - ams AG |
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14 / 31 page ![]() Page 14 ams Datasheet Document Feedback [v2-03] 2014-Jul-31 AS5050A − SPI Inter face SPI Transaction An SPI transaction consists of a 16-bit command frame followed by a 16-bit data frame. Figure 15 shows the structure of the command frame. SPI Command Frame Figure 15: SPI Command Frame To increase the reliability of communication over the SPI, an even parity bit (PAR) must be generated and sent. A wrong setting of the parity bit causes the PARITY bit in the error status register of the AS5050A to be set. The parity bit is calculated from the upper 15-bits of the command frame. The 16-bit command specifies the address and whether the transaction is a read or a write. Bit 15 14 13 12 11 10 9 8 765432 1 0 R/W Address 14:1 PAR Bit Name Description 15 R/W 0=Write, 1=Read 14:1 Address 14 bit address to read or write 0 PAR Parity bit (even) calculated on the upper 15 bits |
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