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ML7344J 데이터시트(PDF) 65 Page - List of Unclassifed Manufacturers |
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ML7344J 데이터시트(HTML) 65 Page - List of Unclassifed Manufacturers |
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65 / 151 page ![]() FEDL7344C/E/J-04 ML7344C/E/J 65/151 (2) Channel #0 frequency setting TX frequency can be set by [TXFREQ_I: B1 0x1B], [TXFREQ_FH: B1 0x1C], [TXFREQ_FM: B1 0x1D] and [TXFREQ_FL: B1 0x1E]. RX frequency can be set by [RXFREQ_I: B1 0x1F], [RXFREQ_FH: B1 0x20], [RXFREQ_FM: B1 0x21] and [RXFREQ_FL: B1 0x22]. When enabling PLL 1/2 division mode by setting PLL_MODE([PLL_DIV_SET:B1 0x1A(4)])=0b1, calcurated with fref =FMCK1/2 in the following formula. Channel #0 frequency setting can be caluculated using the following formula. ref rf f f I = (Integer part) 20 2 ⋅ ⎪⎭ ⎪ ⎬ ⎫ ⎪⎩ ⎪ ⎨ ⎧ − = I f f F ref rf (Integer part) Here rf f :Channel #0 frequency ref f :PLL reference frequency (=master clock frequency: FMCK1) I :Integer part of frequency setting F :Fractional part of frequency setting I (Hex) is set to [TXFREQ_I: B1 0x1B], [RXFREQ_I: B1 0x1F] registers. F (Hex.) is set to the following registers. For TX, from MSB, set in order of [TXFREQ_FH: B1 0x1C], [TXFREQ_FM: B1 0x1D], [TXFREQ_FL: B1 0x1E] registers. For RX, from MSB, set in order of [RXFREQ_FH: B1 0x20], [RXFREQ_FM: B1 0x21], [RXFREQ_FL: B1 0x22] registers. Frequency error ( err f ) is calculated as follows : rf ref err f f F I f − ⋅ ⎭ ⎬ ⎫ ⎩ ⎨ ⎧ + = 20 2 [Example] When set TX channel #0 frequency to 426MHz (master clock 26MHz), the calculations are as follows. MHz MHz I 26 426 = (Integer part) =16(0x10) 20 2 26 426 ⋅ ⎭ ⎬ ⎫ ⎩ ⎨ ⎧ − = I MHz MHz F (Integer part)=403298(0x062762) [TXFREQ_I: B1 0x1B] = 0x10 [TXFREQ _FH: B1 0x1C] = 0x06 [TXFREQ _FM: B1 0x1D] = 0x27 [TXFREQ _FL: B1 0x1E] = 0x62 Frequency error err f is as follows: Hz MHz MHz f err 45 . 11 426 26 2 403298 16 20 − = − ⋅ ⎭ ⎬ ⎫ ⎩ ⎨ ⎧ + = |
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