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ML7344J 데이터시트(PDF) 69 Page - List of Unclassifed Manufacturers

부품명 ML7344J
상세설명  Sub-GHz band short range wireless transceiver IC
PDF  151 Pages
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제조업체  ETC2 [List of Unclassifed Manufacturers]
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ML7344J 데이터시트(HTML) 69 Page - List of Unclassifed Manufacturers

Back Button ML7344J Datasheet HTML 65Page - List of Unclassifed Manufacturers ML7344J Datasheet HTML 66Page - List of Unclassifed Manufacturers ML7344J Datasheet HTML 67Page - List of Unclassifed Manufacturers ML7344J Datasheet HTML 68Page - List of Unclassifed Manufacturers ML7344J Datasheet HTML 69Page - List of Unclassifed Manufacturers ML7344J Datasheet HTML 70Page - List of Unclassifed Manufacturers ML7344J Datasheet HTML 71Page - List of Unclassifed Manufacturers ML7344J Datasheet HTML 72Page - List of Unclassifed Manufacturers ML7344J Datasheet HTML 73Page - List of Unclassifed Manufacturers Next Button
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FEDL7344C/E/J-04
ML7344C/E/J
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(2) FSK modulation setting
By setting GFSK_EN([DATA_SET1: B0 0x07(4)])=0b0, FSK mode can be selected. Fine frequency
deviation can be set by [FSK_DEV0_H/GFIL0: B1 0x32] to [FSK_DEV4_L: B1 0x3B] registers. By adjusting
[FSK_TIM_ADJ4-0: B1 0x3C-40] registers, FSK timing can be fine tuned.
Frequency deviation setting
Timing setting
symbol
Register name
address
function
symbol
Register
name
address
function
I
FSK_FDEV0_H/GFIL0
FSK_FDEV0_L/GFIL1
B1
0x32/33
i
FSK_TIM_ADJ4
B1 0x3C
II
FSK_FDEV1_H/GFIL2
FSK_FDEV1_L/GFIL3
B1
0x34/35
ii
FSK_TIM_ADJ3
B1 0x3D
III
FSK_FDEV2_H/GFIL4
FSK_FDEV2_L/GFIL5
B1
0x36/37
iii
FSK_TIM_ADJ2
B1 0x3E
IV
FSK_FDEV3_H/GFIL6
FSK_FDEV3_L
B1
0x38/39
iv
FSK_TIM_ADJ1
B1 0x3F
V
FSK_FDEV4_H
FSK_FDEV4_L
B1
0x3A/3B
Frequency
deviation
Resolution:
Approx.25
Hz
v
FSK_TIM_ADJ0
B1 0x40
Modulation
timing
4.3MHz/13
MHz
counter
value
(*1)
(*1) Modulation timing resolution can be changed by FSK_CLK_SET ([FSK_CTRL: B1 0x2F(0)]).
NOTE:
GFSK filter coefficient setting register and FSK frequency deviation setting register are common. In GFSK
mode, filter coefficient applies to this register. In FSK mode, frequency deviation applies to this register.
TX_FSK_POL ([DATA_SET1:B0 0x07(6)]) = 0b0 setting
1 output
i
ii
iii
v
I
iv
0 output
i
iii
ii
iv
v
i
iii
ii
iv
i
ii
iii
iv
I
II
II
III
III
IV
IV
V
V



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