L99H01 datasheet(31/53 Pages) STMICROELECTRONICS

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L99H01

Functional description of the SPI

4.1

Signal description

4.1.1

Serial clock (CLK)

This input signal provides the timing of the serial interface. Data present at serial data input

(DI) is latched on the rising edge of serial clock (CLK). Data on Serial Data Out (DO) is

shifted out at the falling edge of serial clock (CLK).

The serial clock CLK must be active only during a frame (CSN low phase). Any other

switching of CLK close to any CSN edge could generate setup/hold violations in the SPI

logic of the device.

4.1.2

Serial data input (DI)

This input is used to transfer data serially into the device. Values are latched on the rising

edge of serial clock (CLK).

4.1.3

Serial data output (DO)

This output signal is used to transfer data serially out of the device. Data is shifted out on the

falling edge of serial clock (CLK).

DO also reflects the status of the <Global Error Flag> (<Global Status Byte>[7]) while CSN

is low and no clock signal is present.

4.1.4

Chip select not (CSN)

When this input signal is high, the communication interface of the device is deselected and

serial data output (DO) is high impedance. Driving this input low enables the

communication. The communication must start and stop on a low-level of serial clock (CLK).

The SPI can be driven by a microcontroller with its SPI peripheral running in following mode:

CPOL = 0 and CPHA = 0.

For timing details and figures refer to Section 2.5.

4.2

General data description

The SPI communication is based on a SPI interface structure using CSN (chip select not),

DI (serial data in), DO (serial data out/error) and CLK (serial clock) signal lines.

Each DI communication frame consists of a <Command Byte> which is followed by 1 <Data

Byte>.

The data returned on DO within the same frame always starts with the <Global Status

Byte>, which provides general status information about the device. This byte is followed by

1 <Data Byte> (‘In-frame-response’).

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