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Copyright © 2010 Future Technology Devices International Limited

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Document Reference No.: FT_000166

V2DIP2-64 VNCL2-64Q Development Module Datasheet Version 1.01

Clearance No.: FTDI# 155

3.6 Parallel FIFO Interface-Asynchronous Mode

The Parallel FIFO Asynchronous mode is functionally the same as the Parallel FIFO Interface present in

VDIP2 has an eight bit data bus, individual read and write strobes and two hardware flow control signals.

3.6.1 Signal Description - Parallel FIFO Interface

The Parallel FIFO Interface signals can be programmed to a choice of available I/O pins.

Table 3.6

shows the Parallel FIFO Interface signals and the pins that they can be mapped.

Available Pins

Name

Type

Description

J2-18, J2-14, J1-17, J1-24, J1-29, J2-

28, J2-23, J1-3, J1-7, J2-8, J2-4

fifo_data[0]

I/O

FIFO data bus Bit 0

J2-17, J1-14, J1-18, J1-26, J1-30, J2-

27, J2-22, J1-4, J1-8, J2-7, J2-3

fifo_data[1]

I/O

FIFO data bus Bit 1

J2-16, J1-15, J1-20, J1-27, J2-30, J2-

26, J1-1, J1-5, J1-9, J2-6, J2-2

fifo_data[2]

I/O

FIFO data bus Bit 2

J2-15, JI-16, J1-21, J1-28, J2-29, J2-24,

J1-2, J1-6, J2-9, J2-5, J2-1

fifo_data[3]

I/O

FIFO data bus Bit 3

J2-14, J1-17, J1-24, J1-29, J2-28, J2-

23, J1-3, J1-7, J2-8, J2-4

fifo_data[4]

I/O

FIFO data bus Bit 4

J2-17, J1-14, J1-18, J1-26, J1-30, J2-

27, J2-22, J1-4, J1-8, J2-7, J2-3

fifo_data[5]

I/O

FIFO data bus Bit 5

J2-16, J1-15, J1-20, J1-27, J2-30, J2-

26, J1-1, J1-5, J1-9, J2-6, J2-2

fifo_data[6]

I/O

FIFO data bus Bit 6

J2-15, JI-16, J1-21, J1-28, J2-29, J2-24,

J1-2, J1-6, J2-9, J2-5, J2-1

fifo_data[7]

I/O

FIFO data bus Bit 7

J2-14, J1-17, J1-24, J1-29, J2-28, J2-

23, J1-3, J1-7, J2-8, J2-4

fifo_rxf#

Output

When high, do not read data

from the FIFO. When low, there

is data available in the FIFO

which can be read by strobing

RD# low, then high.

J2-17, J1-14, J1-18, J1-26, J1-30, J2-

27, J2-22, J1-4, J1-8, J2-7, J2-3

fifo_txe#

Output

When high, do not write data into

the FIFO. When low, data can be

written into the FIFO by strobing

fifo_wr# high, then low.

J2-16, J1-15, J1-20, J1-27, J2-30, J2-

26, J1-1, J1-5, J1-9, J2-6, J2-2

fifo_rd#

Input

Enables the current FIFO data

byte on D0...D7 when low.

Fetches the next FIFO data byte

(if available) from the receive

FIFO buffer when fifo_rd# goes

from high to low

J2-15, JI-16, J1-21, J1-28, J2-29, J2-24,

J1-2, J1-6, J2-9, J2-5, J2-1

fifo_wr#

Input

Writes the data byte on the

D0...D7 pins into the transmit

FIFO buffer when fifo_wr# goes

from high to low.

Table 3.6 - Data and Control Bus Signal Mode Options – Parallel FIFO Interface