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Copyright © 2010 Future Technology Devices International Limited

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Document Reference No.: FT_000166

V2DIP2-64 VNCL2-64Q Development Module Datasheet Version 1.01

Clearance No.: FTDI# 155

Appendix B – List of Figures and Tables

List of Figures

Figure 1.1 - V2DIP2-64 .................................................................................................................1

Figure 3.1 - V2DIP2-64 Module Pin Out (Top View) ..........................................................................4

Figure 3.3 – Asynchronous FIFO Mode Read and Write Cycle............................................................ 13

Figure 3.4 - Synchronous FIFO Mode Read and Write Cycle.............................................................. 14

Figure 5.1 - V2DIP2 -64 Dimensions (Top View) ............................................................................. 18

Figure 5.2 - V2DIP2 -64 Dimensions (Side View) ............................................................................ 18

Figure 6.1 - V2DIP2 -64 Dimensions (Side View) ............................................................................ 19

List of Tables

Table 3.1 - Pin Signal Descriptions ..................................................................................................6

Table 3.2 - Default Interface I/O Pin Configuration...........................................................................8

Table 3.3 - Data and Control Bus Signal Mode Options – UART ......................................................... 10

Table 3.4 - Data and Control Bus Signal Mode Options – SPI Slave ................................................... 11

Table 3.5 - Data and Control Bus Signal Mode Options – SPI Master ................................................. 11

Table 3.6 - Data and Control Bus Signal Mode Options – Parallel FIFO Interface ................................. 12

Table 3.7 Asynchronous FIFO Mode Read Cycle Timing .................................................................... 13

Table 3.8 - Data and Control Bus Signal Mode Options – Synchronous FIFO mode .............................. 14

Table 3.9 - Synchronous FIFO Mode Read and Write Cycle Timing .................................................... 15

Table 3.10 - Signal Name and Description – Debugger Interface....................................................... 16