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GDC21D301A 데이터시트(PDF) 4 Page - Hynix Semiconductor |
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GDC21D301A 데이터시트(HTML) 4 Page - Hynix Semiconductor |
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4 / 35 page ![]() 5 GDC21D301A 1. General Description The GDC21D301A Transport Decoder resides in the center of an MPEG-2 decoding system. It accepts MPEG-2 transport streams, parses the transport and packetized elementary stream (PES) layers into the separate data streams, and provides rate buffering for the parsed data streams. Then it passes those data streams to video and audio decoders. The GDC21D301A also extracts Program Clock Reference (PCR) in the data stream and provides the Pulse Width Modulation (PWM) signals in order to recover the clock and to synchronize the playback of video and audio. The GDC21D301A manages an external DRAM that is used for data storage and buffering the various parsed data streams. This DRAM is shared with the host processor so that the system’s memory requirements can be consolidated into a single, low-cost DRAM. The GDC21D301A stores data packets destined for the host directly in shared DRAM for easy access by the host. 2. Features The GDC21D301A is fully compliant with MPEG- 2 ISO/IEC 13818-1 specification. Decoding Features • Performs MPEG-2 transportation and PES layer handling • Supports maximum 80 Mbps transport streams • Provides a high-speed data output port • Identifies and extracts up to 32 transport stream (TS) packet PIDs PCR & Time Stamp Control Features • Provides two PWM signals to recover the system clock • Provides the instant value of internal STC counter when a frame begins • Extracts PTS and DTS of video and audio for Lip-synchronization Interface • Supports byte-parallel/bit-serial TS input • Supports video/audio PES layer or elementary stream layer output • Provides error code insertion capability in video elementary stream • Supports an external error input signal for declaring an erroneous packet • Supports 8/16-bit host bus interface GDC21D301A Transport Decoder |
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