2

AV9172

Pin Configuration

Pin Description for AV9172-01

16-Pin SOIC or 16-Pin PDIP

Functionality Table for AV9172-01

CLKIN input frequency range 10 to 50 MHz.

Notes:

1. 1X designates that the output is a replica of CLKIN.

2. 2X designates that the output is twice the frequency of

CLKIN, and in phase.

3. 1X# means that the output is at the same frequency and

180°C out of phase (inverted) from CLKIN.

4. Ø1 will produce a ¼ duty cycle clock of CLKIN.

5. Ø2 will produce a ¼ duty cycle clock delayed 180° from

CLKIN.

EN2

INV#

Q0

Q1

Q2

Q3

Q4

Q5

0

0

1X

1X#

2X

2X

2X

2X

0

1

1X

1X

2X

2X

2X

2X

1

0

1X

1X#

2X

2X

1

1

1X

1X

2X

2X

PIN NUMBER

PIN NAME

TYPE

DESCRIPTION

1

GND

-

GROUND.

2

GND

-

GROUND.

3

INV#

Input

INV# Inverts Q1 when low. (-01 [divisor select -03, -07])

4

EN

Input

EN converts Q4 and Q5 to phase clocks when high.

5

FBIN

Input

FEEDBACK INPUT from output Q0.

6

CLKIN

Input

INPUT for reference clock.

7

VDD

-

Power supply (+5V).

8

VDD

-

Power supply (+5V).

9

GND

-

GROUND.

10

Q0

Output

Q0 phase and frequency same as input (1X). Feed back to pin 5.

11

Q1

Output

Q1 is a 1x clock in phase or 180° out of phase with input.

12

Q2

Output

Q2 twice the frequency of Q0 (2x).

13

Q3

Output

Q3 twice the frequency of Q0 (2x).

14

Q4

Output

Q4 is either a 2X clock or a two-phase clock - see configuration table.

15

Q5

Output

Q5 is either a 2X clock or a two-phase clock - see configuration table.

16

VDD

-

Power supply (+5V).