AT697F_14 datasheet(5/176 Pages) ATMEL

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AT697F

7703E–AERO–08/11

These signals carry the EDAC checkbits(1) during a write access to the external memory

and are kept in high impedance otherwise. This applies whatever the EDAC activation

or not.

Note:

1. While only 7 bits are useful for EDAC protection, CB[7] is implemented to enable

programming of FLASH memories and takes the value of MCFG3.tcb[7].

OE* - Output enable (output)

This active low output is asserted during a read access to the external memory. It can

be used as an output enable signal when accessing PROM & I/O devices.

READ - Read enable (output)

This active high output is asserted during a read access to the external memory. It can

be used as a read enable signal when accessing PROM & I/O devices.

WRITE* - Write enable (output)

This active low output is asserted during a write-access to the external memory. It can

be used as a write enable signal when accessing PROM & I/O devices.

RWE*[3:0] - PROM & SRAM byte write-enable (output)

These active low outputs provide individual write strobes for each byte-lane on the data

bus: RWE*[0] controls D[31:24], RWE*[1] controls D[23:16], RWE*[2] controls

D[15:8] and RWE*[3] controls D[7:0], and they are set according to the transaction

width (word/half-word/byte) and the bus width set for the respective area.

BRDY* - Bus ready (input)

When driven low, this input indicates to the processor that the current memory access

can be terminated on the next rising clock edge. When driven high, this input indicates

to the processor that it must wait and not end the current access.

PROM

ROMS*[1:0] - PROM chip-select (output)

These active low outputs provide the chip-select signals for decoding the PROM area.

ROMS*[0] is asserted when the lower half of the PROM area is accessed

(0x00000000 - 0x0FFFFFFF), while ROMS*[1] is asserted when the upper half is

accessed (0x10000000 - 0x1FFFFFFF).

SRAM

RAMS*[4:0] - SRAM chip-select (output)

These active low outputs provide the chip-select signals for decoding five SRAM banks.

RAMOE*[4:0] - SRAM output enable (output)

These active low signals provide an output enable signal for each SRAM bank.

I/O

IOS* - I/O select (output)

This active low output provides the chip-select signal for decoding the memory mapped

I/O area.

SDRAM

SDCLK - SDRAM clock (output)

This signal provides a reference clock for SDRAM memories. It is a copy of the proces-

sor internal clock.

SDCS*[1:0] - SDRAM chip select (output)

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