2

ICS9147-09

Pin Descriptions

* Bidirectional input/output pins, input logic level determined at internal power-on-reset are latched. Use 10Kohm resistor to

program logic Hi to VDD or GND for logic low.

PIN NUMBER

PIN NAME

TYPE

DESCRIPTION

2

REF

OUT

Reference clock output*

FS1

IN

Logic input frequency select Bit1*. Input latched at Poweron.

3, 9, 16, 22,

27, 33, 39, 45

GND

PWR

Ground.

4

X1

IN

Crystal input. Nominally 14.318 MHz. Has internal load cap

5

X2

OUT

Crystal output. Has internal load cap and feedack resistor to X1

41

VDDL

PWR

2.5 or 3.3V buffer power for CPUL and IOAPIC output buffers.

8, 10, 11, 12, 14,

BUS (1:5)

OUT

BUS clock outputs. see select table for frequency

15

BUS6

OUT

BUS clock output. See select table for frequency.*

FS0

IN

Logic input frequency select Bit0.*. Input latched at Poweron.

23

CPU_STOP#

IN

Halts CPU Clocks at Logic "0" level when low. Internal Pull-up

24

PD#

IN

Powers down chip, active low. Internal Pull-up

47

24M

OUT

24MHz fixed clock.*

BSEL

IN

Logic input* for selecting synchronous or asynchronous BUS

frequency- see table above. Input latched at Poweron.*

1, 6, 13, 19,

30, 36, 48

VDD3

PWR

3.3 volt core logic and buffer power

17, 18, 20, 21, 28,

29, 31, 32, 34,

35, 37, 38

SDRAM (1:12)

OUT

SDRAM clocks at CPU speed. See select table for frequency.

40

CPUH/AGP

OUT

CPU clock operates at SDRAM VDD level (3.3V nom), for AGP etc.

42, 43

CPUL (1:2)

OUT

CPU clocks .See select table for frequency. Operates at down to

2.5V controlled by VDDL pin.

7, 25, 26

N/C

—

Pins not internally connected.

46

48M

OUT

48 MHz fixed clock output*.

FS2

IN

Logic input frequency select Bit 2*. Input latched at Poweron.

44

IOAPIC

OUT

Reference clock (14.318MHz) powered by VDDL,

operating 2.5 to 3.3V.