6

ICS9250-29

Byte 2: Control Register

(1 = enable, 0 = disable)

Notes:

1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at

power-on and are not expected to be configured during the normal modes of operation.

2. PWD = Power on Default

3. Undefined bits can be written with either "1" or "0"

t

i

B#

n

i

Pe

m

a

ND

W

Pn

o

i

t

p

i

r

c

s

e

D

7

t

i

B2

1)

P

G

A

(

2

_

6

6

V

31

)

e

v

i

t

c

a

n

I

/

e

v

i

t

c

A

(

6

t

i

B1

32

1

M

A

R

D

S1

)

e

v

i

t

c

a

n

I

/

e

v

i

t

c

A

(

5

t

i

B4

31

1

M

A

R

D

S1

)

e

v

i

t

c

a

n

I

/

e

v

i

t

c

A

(

4

t

i

B5

30

1

M

A

R

D

S1

)

e

v

i

t

c

a

n

I

/

e

v

i

t

c

A

(

3

t

i

B8

39

M

A

R

D

S1

)

e

v

i

t

c

a

n

I

/

e

v

i

t

c

A

(

2

t

i

B9

38

M

A

R

D

S1

)

e

v

i

t

c

a

n

I

/

e

v

i

t

c

A

(

1

t

i

B5

11

K

L

C

I

C

P1

)

e

v

i

t

c

a

n

I

/

e

v

i

t

c

A

(

0

t

i

B-

t

i

b

d

e

n

i

f

e

d

n

U0

)

e

v

i

t

c

a

n

I

/

e

v

i

t

c

A

(

Byte 3: ICS Reserved Functionality and frequency select register (Default as noted in PWD)

Note 1: For system operation, the BSEL lines of the CPU will program FS0, FS1 for the appropriate CPU speed, always with

SDRAM = 100MHz. After BIOS verifies the SDRAM is PC133 speed, then bit 0 can be written from the default 0 to 1

to change the SDRAM output frequency from 100MHz to 133MHz. This will only change if the CPU is at the

133MHz FSB speed as shown in this table. The CPU, 3V66, PCI and IOAPIC clocks will be glitch free during this

transition, and only SDRAM will change.

Note 2: Must be written with "0"

Note 3: Undefined bits can be written with either "1" or "0"

t

i

Bn

o

i

t

p

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r

c

s

e

DD

W

P

7

t

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N

(

t

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b

d

e

v

r

e

s

e

R

S

C

I

0

6

t

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B)

2

e

t

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N

(

t

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b

d

e

v

r

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s

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R

S

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I

0

5

t

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2

e

t

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N

(

t

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b

d

e

v

r

e

s

e

R

S

C

I

0

4

t

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B)

2

e

t

o

N

(

t

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b

d

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v

r

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s

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I

0

3

t

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l

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n

=

0

/

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5

=

1

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5

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2

t

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3

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1

1

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)

#

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t

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t

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i

r

T

=

0

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#

N

D

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W

P

=

1

(

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N

D

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W

P

/

#

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t

a

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T

1

0

t

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0

t

i

B1

S

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S

F

K

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C

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P

C

z

H

M

M

A

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D

S

z

H

M

6

6

V

3

z

H

M

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C

I

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P

z

H

M

C

I

P

A

O

I

z

H

M

0

1

e

t

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N

000

6

6

.

6

60

.

0

0

16

6

.

6

63

3

.

3

33

3

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3

3

00

1

0

.

0

0

10

.

0

0

16

6

.

6

63

3

.

3

33

3

.

3

3

01

0

2

3

.

3

3

12

3

.

3

3

16

6

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6

63

3

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3

33

3

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3

3

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1

2

3

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3

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6

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6

63

3

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3

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3

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3

3

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6

6

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6

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6

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63

3

.

3

33

3

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3

3

10

1

0

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0

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0

16

6

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6

63

3

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3

33

3

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3

3

11

0

2

3

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3

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3

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3

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6

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3

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3

33

3

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3

3

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2

3

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3

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3

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3

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