Integrated

Circuit

Systems, Inc.

ICS9250-29

Third party brands and names are the property of their respective owners.

Block Diagram

9250-29 Rev A 02/01/01

Recommended Application:

Solano type chipset.

Output Features:

•

2 CPU (2.5V) (up to 133MHz achievable through I

•

13 SDRAM (3.3V) (up to 133MHz achievable

through I

•

5 PCI (3.3 V) @33.3MHz

•

1 IOAPIC (2.5V) @ 33.3 MHz

•

3 Hublink clocks (3.3 V) @ 66.6 MHz

•

2 (3.3V) @ 48 MHz (Non spread spectrum)

•

1 REF (3.3V) @ 14.318 MHz

Features:

•

Supports spread spectrum modulation,

0 to -0.5% down spread.

•I

•

Efficient power management scheme through PD#

•

Uses external 14.138 MHz crystal

•

Alternate frequency selections available through I

control.

Functionality

Pin Configuration

56-Pin 300mil SSOP

* This input has a 50K

9 pull-down to GND.

** This input has a 50K

9pull-up to VDD

IOAPIC

VDDL

GNDL

*FS1/REF

VDDR

X1

X2

GNDR

VDD3

3V66-0

3V66-1

3V66-2

GND3

PCICLK0

PCICLK1

PCICLK2

VDD2

GND2

PCICLK3

PCICLK4

FS0

GNDA

VDDA

SCLK

SDATA

GNDF

VDDF

48MHz_0

GNDL

VDDL

CPUCLK0

CPUCLK1

GND1

SDRAM0

SDRAM1

VDD1

GND1

SDRAM2

SDRAM3

SDRAM4

SDRAM5

VDD1

GND1

SDRAM6

SDRAM7

SDRAM8

SDRAM9

VDD1

GND1

SDRAM10

SDRAM11

VDD1

GND1

SDRAM12

TRISTATE#/PD#**

48MHz_1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

Frequency Generator & Integrated Buffers for Celeron & PII/III™

REF

CPU66/100/133 [1:0]

VDDL

3V66 [2:0]

SDRAM [12:0]

PCICLK [4:0]

IOAPIC

VDDL

PLL2

48MHz [1:0]

X1

X2

XTAL

OSC

Control

Logic

Config

Reg

FS(1:0)

PD#

TRISTATE#

2

2

3

13

5

/2

/2

/3

/2

PLL1

Spread

Spectrum

SDATA

SCLK

#

e

t

a

t

s

i

r

T0

S

F1

S

F

U

P

C

z

H

M

M

A

R

D

S

z

H

M

00

X

e

t

a

t

s

i

r

Te

t

a

t

s

i

r

T

01

X

t

s

e

Tt

s

e

T

10

0

z

H

M

6

6z

H

M

0

0

1

11

0

z

H

M

0

0

1z

H

M

0

0

1

10

1

z

H

M

3

3

1z

H

M

3

3

1

11

1

z

H

M

3

3

1z

H

M

0

0

1

ICS reserves the right to make changes in the device data identified in this

publication without further notice. ICS advises its customers to obtain the

latest version of all device data to verify that any information being relied

upon by the customer is current and accurate.

Power Groups

VDDA, GNDA = CPU, PLL (analog)

VDDF, GNDF = Fixed PLL, 48M (analog/digital)

VDDR, GNDR = REF, X1, X2 (analog/digital)

VDD3, GND3 = 3V66 (digital)

VDD2, GND2 = PCI (digital)

VDD1, GND1 = SDRAM (digital)

VDDL, GNDL = IOAPIC, CPU (digital)