| 전자부품 데이터시트 검색엔진 |
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8X930AX 데이터시트(PDF) 18 Page - Intel Corporation |
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8X930AX 데이터시트(HTML) 18 Page - Intel Corporation |
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18 / 38 page ![]() 14 ADVANCE INFORMATION 8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER I TL Logical 1-to-0 Transition Current (Port 1, 2,3) -650 µA V IN = 2.0 V R RST RST Pulldown Resistor 40 225 K Ω C IO 10 pF F OSC = 12 MHz T A = 25°C I PD Powerdown Current — Normal powerdown — USB suspend 25 145 50 175 µA I DL (5) Idle Mode I CC 40 mA PLLSEL = 110 3MHz – FS (in low clock mode) 100 PLLSEL = 110 12MHz – FS (not in low clock mode) 30 PLLSEL = 001 3MHz – LS 55 PLLSEL = 100 6 MHz – LS Table 9. DC Characteristics at Operating Conditions (Continued) Symbol Parameter Min Typical (1) Max Units Test Conditions NOTE: 1. Typical values are obtained using V CC = 5.0V, TA = 25°C and are not guaranteed. 2. Under steady state (non-transient) conditions, I OL must be externally limited as follows: Maximum I OH per port pin:10 mA Maximum I OL per 8-bit port: Port 0: 26 mA Ports 1-3: 15 mA Maximum Total I OL for all output pins: 71 mA If I OL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 3. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level outputs of ALE and Ports 1, 2 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins change from 1 to 0. In applications where capacitive loading exceeds 100pF, the noise pulses on these signals may exceed 0.8 V. It may be desirable to qualify ALE or other signals with a Schmitt Trigger or CMOS-level input logic. 4. Capacitive loading on Ports 0 and 2 cause the V OH on ALE and PSEN to drop below the VCC specifica- tion when the address lines are stabilizing. 5. The abbreviations “LS” and “FS” indicate “Low Speed” and “Full Speed,” respectively. |
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