8XC196KB datasheet(2/17 Pages) INTEL

2 / 17 page

AUTOMOTIVE 8XC196KB

270679 – 3

Figure 2 The 8XC196KB Family Nomenclature

ARCHITECTURE

The 8XC196KB is a member of the 8096 family as

such has the same architecture and uses the same

instruction set as the 8096 Many new features have

been added on the 8CX196KB including

CPU FEATURES

Divide by 2 instead of divide by 3 clock for a 15c

performance improvement

Faster instructions especially indexedindirect data

operations

1725 ms 16 x 16 multiply with 16 MHz clock (is

625 ms on the 8096)

Faster interrupt response (almost twice as fast)

Powerdown and Idle Modes

6 new instructions

8 new interrupt vectors6 new interrupt sources

PERIPHERAL FEATURES

SFR window switching allows read-only SFRs to be

written and vice-versa

Timer 2 can count up and down by external selec-

tion

Timer 2 has an independent capture register on ris-

ing edges of (P27)

HSO line events are stored in a register

HSO has CAM lock and CAM clear commands

New baud rate values are needed for serial port

which enables higher speeds in all modes

Double buffered serial port transmit register (before

only receive was double buffered)

Serial port receive overrun and framing error detec-

tion

PWM has a divide by 2 prescaler

HOLDHLDA bus protocol

THERMAL CHARACTERISTICS

PLCC

iJA

35 CW

iJC

12 CW

Max Case

135 C

Temperature

NEW INSTRUCTIONS

PUSHA

PUSHes the PSW IMASK IMASK1 and

WSR (used instead of PUSHF when us-

ing the new interrupts and registers)

POPA

POPs the PSW IMASK IMASK1 and

WSR (used instead of POPF when using

the new interrupts and registers)

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