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CDP1823CDX 데이터시트(PDF) 4 Page - Intersil Corporation

부품명 CDP1823CDX
상세설명  128-Word x 8-Bit LSI Static RAM
PDF  7 Pages
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제조업체  INTERSIL [Intersil Corporation]
홈페이지  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

CDP1823CDX 데이터시트(HTML) 4 Page - Intersil Corporation

  CDP1823CDX Datasheet HTML 1Page - Intersil Corporation CDP1823CDX Datasheet HTML 2Page - Intersil Corporation CDP1823CDX Datasheet HTML 3Page - Intersil Corporation CDP1823CDX Datasheet HTML 4Page - Intersil Corporation CDP1823CDX Datasheet HTML 5Page - Intersil Corporation CDP1823CDX Datasheet HTML 6Page - Intersil Corporation CDP1823CDX Datasheet HTML 7Page - Intersil Corporation  
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Dynamic Electrical Specifications At TA = -40 to +85oC, VDD ±5%, tR, tF = 20ns, CL = 100pF
PARAMETER
SYMBOL
VDD
(V)
LIMITS
CDP1823
CDP1823C
UNITS
(NOTE 2)
MIN
(NOTE 1)
TYP
MAX
(NOTE 2)
MIN
(NOTE 1)
TYP
MAX
Read Cycle (See Figure 1)
Access Time From Address
Change
tAA
5
-
275
450
-
275
450
ns
10
-
150
250
-
-
-
ns
Access Time From Chip
Select
tDOA
5
-
150
250
-
150
250
ns
10
-
100
150
-
-
-
ns
MRD to Output Active
tAM
5
-
150
250
-
150
250
ns
10
-
100
150
-
-
-
ns
Data Hold Time After Read
tDOH
5
255075255075
ns
10
15
25
40
-
-
-
ns
NOTES:
1. Typical values are at TA = 25
oC and nominal voltage.
2. Time required by a limit device to allow for the indicated function.
ADDRESS
tAA
tAM
tDOA
tDOH
MRD
CS2, CS3, CS5
CS1, CS4
DATA OUT
HIGH IMPEDANCE
VALID DATA
90%
10%
NOTE:
1. MWR is high during read operation. Timing measurement reference is 0.5 VDD.
FIGURE 1. READ CYCLE TIMING DIAGRAM
CDP1823, CDP1823C



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