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CDP1823CDX 데이터시트(PDF) 6 Page - Intersil Corporation

부품명 CDP1823CDX
상세설명  128-Word x 8-Bit LSI Static RAM
PDF  7 Pages
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제조업체  INTERSIL [Intersil Corporation]
홈페이지  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

CDP1823CDX 데이터시트(HTML) 6 Page - Intersil Corporation

  CDP1823CDX Datasheet HTML 1Page - Intersil Corporation CDP1823CDX Datasheet HTML 2Page - Intersil Corporation CDP1823CDX Datasheet HTML 3Page - Intersil Corporation CDP1823CDX Datasheet HTML 4Page - Intersil Corporation CDP1823CDX Datasheet HTML 5Page - Intersil Corporation CDP1823CDX Datasheet HTML 6Page - Intersil Corporation CDP1823CDX Datasheet HTML 7Page - Intersil Corporation  
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Data Retention Specifications At TA = -40 to +85oC, see Figure 3
PARAMETER
TEST
CONDITIONS
LIMITS
UNITS
CDP1823
CDP1823C
VDR
(V)
VDD
(V)
MIN
(NOTE 1)
TYP
MAX
MIN
(NOTE 1)
TYP
MAX
Minimum Data Retention Voltage,
VDR
-
-
-
1.5
2
-
1.5
2
V
Data Retention Quiescent Current, IDD
2
-
-
30
100
-
30
100
µA
Chip Deselect to Data Retention Time
-
5
600
-
-
600
-
-
ns
tCDR
-
10
300
--
--
-
ns
Recovery to Normal Operation
Time
tRC
-
5
600
-
-
600
-
-
ns
-
10
300
--
--
-
ns
VDD to VDR Rise and Fall Time
tR, tF
25
1
-
-
1
-
-
µs
NOTE:
Typical values are for TA = 25
oC and nominal V
DD.
FIGURE 3. LOW VDD DATA RETENTION TIMING WAVEFORMS
FIGURE 4. FUNCTIONAL DIAGRAM
0.95 VDD
VDD
tCDR
CS1
VIH
VIL
tRC
VIH
VIL
0.95 VDD
VDR
DATA RETENTION
MODE
tF
tR
MA0
BUFFER
AND
DECODER
BUFFER
CONTROL
DECODER
16 x 8 x 8
STORAGE
ARRAY
MA1
MA2
MA3
MA4
MA5
MA6
MRD
MWR
CS1
CS3
CS2
CS4
CS5
BUS 0-7
CDP1823, CDP1823C



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