4-101

FIGURE 11. TYPICAL CDP1802 INPUT/OUTPUT-MAPPED SYSTEM

CLOCK

CLEAR

TPA

MRD

TPB

N0

N1

N2

INT

XTAL

CDP1802

MEMORY

COUNTER - TIMER

DB0 - DB7

DATA BUS

ADDRESS

LINES

RESET

TPA

RD

TPB/WR

A0

A1

A2

CS

INT

IO/MEM

TACL, TBCL

TBG

TAO

TAO

TBO

TBO

TAG

GATE

TIMER

INPUTS

OUTPUTS

FIGURE 12. CDP1800-SERIES INPUT/OUTPUT-MAPPING TIMING WAVEFORMS WITH OUTPUT INSTRUCTION

VALID DATA

DATA FROM MEMORY

N LINES

RD

TPA

TO COUNTER-TIMER

TPB/WR

DATA LATCHED

FIGURE 13. CDP1800-SERIES INPUT/OUTPUT-MAPPING TIMING WAVEFORMS WITH INPUT INSTRUCTION

VALID DATA

OUTPUT DRIVERS ENABLED

OUTPUT DRIVERS

DISABLED

DATA FROM

RD

TPB/WR

TPA

COUNTER-TIMER

TO MEMORY

N LINES

CDP1878C