CDP1878CD datasheet(3/13 Pages) INTERSIL

3 / 13 page

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Functional Diagram

FUNCTIONAL DEFINITIONS FOR CDP1878C TERMINALS

TERMINAL

USAGE

TERMINAL

USAGE

VDD - VSS

Power

TAO, TAO

Complemented outputs of Timer A

DB0-DB7

Data to and from device

TBO, TBO

Complemented outputs of Timer B

TPB/WR, RD

Directional Control Signals

TPA

Used with CDP1800-series processors, tied high

otherwise

A0, A1, A2

Addresses that select counters or registers

Active high input that enables device

TACL, TBCL

Clocks used to decrement counters

INT

Low when counter is “0”

TAG, TBG

Gate inputs that control counters

RESET

When active, TAO, TBO are low, TAO, TBO are

high. Interrupt status register is cleared.

IO/MEM

Tied high in CDP1800 input/output mode, other-

wise tied low

RESET

TPB/WR

IO/MEM

TPA

VDD

VSS

I-O

CONTROL

AND

LOGIC

DATA

BUS

DRIVERS

8-BIT

EXTERNAL

BUS

JAM

HOLDING

JAM

COUNTER A

COUNTER B

CONTROL REGISTER B

AND MODE CONTROL

INT AND

STATUS REGISTER

CONTROL REGISTER A

AND MODE CONTROL

INT

GATE A

TAO

CLOCK A

GATE B

TBO

CLOCK B

CDP1878C

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