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ADF4112BCPZ 데이터시트(PDF) 16 Page - Analog Devices

부품명 ADF4112BCPZ
상세설명  RF PLL Frequency Synthesizers
PDF  28 Pages
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제조업체  AD [Analog Devices]
홈페이지  http://www.analog.com
Logo AD - Analog Devices

ADF4112BCPZ 데이터시트(HTML) 16 Page - Analog Devices

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ADF4110/ADF4111/ADF4112/ADF4113
Data Sheet
Rev. F | Page 16 of 28
Table 8. AB Counter Latch Map
THESE BITS ARE NOT USED
BY THE DEVICE AND ARE
DON'T CARE BITS
A6
0
0
0
0
•
•
•
1
1
1
1
A5
0
0
0
0
•
•
•
1
1
1
1
A2
0
0
1
1
•
•
•
0
0
1
1
A1
0
1
0
1
•
•
•
0
1
0
1
A COUNTER
DIVIDE RATIO
0
1
2
3
•
•
•
60
61
62
63
••••••••• •
••••••••• •
••••••••• •
••••••••• •
••••••••• •
••••••••• •
••••••••• •
••••••••• •
••••••••• •
••••••••• •
••••••••• •
••••••••• •
B13
0
0
0
0
0
•
•
•
1
1
1
1
B12
0
0
0
0
0
•
•
•
1
1
1
1
B11
0
0
0
0
0
•
•
•
1
1
1
1
B3
B2
B1
B COUNTER DIVIDE RATIO
••••••••• •
••••••••• •
••••••••• •
••••••••• •
••••••••• •
••••••••• •
••••••••• •
••••••••• •
••••••••• •
••••••••• •
••••••••• •
••••••••• •
••••••••• •
0
0
0
0
1
•
•
•
1
1
1
1
0
0
1
1
0
•
•
•
0
0
1
1
0
1
0
1
0
•
•
•
0
1
0
1
NOT ALLOWED
NOT ALLOWED
NOT ALLOWED
3
4
•
•
•
8188
8189
8190
8191
13-BIT B COUNTER
DB23 DB22
DB21 DB20
DB19 DB18
DB17 DB16
DB15 DB14
DB12
DB11 DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB13
B13
B12
B11
B8
B7
B6
B5
B4
B2
B1
A6
A5
A4
A3
A2
A1
B3
6-BIT A COUNTER
RESERVED
DB2
G1
B10
B9
*SEE TABLE 9
F4 (FUNCTION LATCH)
FASTLOCK ENABLE*
CP GAIN
OPERATION
0
0
1
1
0
1
0
1
CHARGE PUMP CURRENT SETTING 1
IS PERMANENTLY USED.
CHARGE PUMP CURRENT SETTING 2
IS PERMANENTLY USED.
CHARGE PUMP CURRENT SETTING 1
IS USED.
CHARGE PUMP CURRENT IS SWITCHED
TO SETTING 2. THE TIME SPENT IN
SETTING 2 IS DEPENDENT UPON WHICH
FASTLOCK MODE IS USED. SEE FUNCTION
LATCH DESCRIPTION.
N = BP + A, P IS PRESCALER VALUE SET IN THE
FUNCTION LATCH, B MUST BE GREATER THAN OR
EQUAL TO A. FOR CONTINUOUSLY ADJACENT VALUES
OF (NX FREF), AT THE OUTPUT, NMIN IS (P2–P).
X
X = DON'T CARE
X
C2 (0) C1 (1)
CONTROL
BITS
DB1
DB0



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