UPD16675AP datasheet(13/36 Pages) NEC

13 / 36 page

µµµµPD16675A

COMMAND

5.1

Basic Form

Chip address register (CAR)





















Command register (CR)

Address register (AR)

X address (XAD)

Data 1 (DT1)

Data 2 (DT2)

+ • •

5.2

Chip Address Register (CAR)

00000

b2 b1 b0

Chip address

000: CS2 = 0, CS1 = 0, and CSo = 0 ICs accessible

001: CS2 = 0, CS1 = 0, and CSo = 1 ICs accessible

010: CS2 = 0, CS1 = 1, and CSo = 0 ICs accessible

011: CS2 = 0, CS1 = 1, and CSo = 1 ICs accessible

100: CS2 = 1, CS1 = 0, and CSo = 0 ICs accessible

101: CS2 = 1, CS1 = 0, and CSo = 1 ICs accessible

110: CS2 = 1, CS1 = 1, and CSo = 0 ICs accessible

111: CS2 = 1, CS1 = 1, and CSo = 1 ICs accessible

MSB

LSB

The register is made valid in the following states.

Interface

CAE

High level

Low level

Serial

Valid

Invalid

4-bit parallel

Valid

Invalid

8-bit parallel

Valid (CAE: Used as the D6 bit)

It is unnecessary to transmit the register that is invalid.

UPD16675AP 데이터시트(PDF) 13 Page - NEC

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