AN3316 datasheet(21/42 Pages) STMICROELECTRONICS

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AN3316

Device modes

Doc ID 18232 Rev 2

21/42

For the HW steps, refer to Section : Common HW aspects. Now, see in details the

operations done for each phase:

DRUN mode:

XTAL config

–

CGM.OSC_CTL.EOCV = xxx (set stabilization counter)

FMPLL config:

PLL freq is done by the following formula:

Where:

–

clkin = reference clock = XTAL at 8 MHz

–

LDF (NDIV) is the Loop Divided Ratio with this configurations:

–

IDF is the Input Divided Ratio with following configurations:

–

ODF is the Output Divided Ratio with following configurations:

Table 3.

Loop divide ratio

NDIV[6:0]

Loop divide ratios

0000000-0011111

0100000

Divide by 32

0100001

Divide by 33

0100010

Divide by 34

...

1011111

Divide by 95

1100000

Divide by 96

1100001-1111111

Table 4.

Input divide ratio

IDF[3:0]

Input divide ratios

0000

Divide by 1

0001

Divide by 2

0010

Divide by 3

...

1110

Divide by 15

phi

clkin LDF



IDF ODF



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