AN4253 datasheet(25/44 Pages) STMICROELECTRONICS

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AN4253

HW resource initialization

It is recommended to split clock subsystem setup to several parts to make the clock

transition safe with minimum impact on voltage regulator load. All mode transitions issued

here use DRUN mode as a target mode.

Configure oscillator module

Enable oscillator block (mode transition)

Configure input clock to FMPLL0

Configure FMPLL0

Enable FMPLL0 block (mode transition)

Wait for FMPLL0 lock

Enable peripherals needed in the startup (clock gating)

Switch system clock to FMPLL0 output (mode transition)

Configure oscillator block

Here one parameter shall be tuned with respect to ECU design and selected crystal

oscillator. It is end of count value parameter, EOCV bit field in RC_CTL register.

EOCV value shall satisfy the following formula:

EOCV >= (TXOSCHSSU * fXOSCHS) / 512

where fXOSCHS is the "oscillator frequency" and TXOSCHSSU is the "oscillator start-up

time" whose value can be found in the DS.

Default reset value

Code sequence

Write required value to EOCV bit field in OSC_CTL register

Enable oscillator block (mode transition)

In order to enable the crystal oscillator block, mode transition is required with bit XOSCON

in ME_DRUN_MC register set on.

Code sequence

Set bit XOSCON in ME_DRUN_MC register

Write DRUN with Key_1 in ME_MCTL register

Write DRUN with Key_2 in ME_MCTL register

Wait mode transition to finish (ME_GS.MTRANS bit = 0)

•

Count value to reach =

EOCV*512

This parameter tells how many clock pulses will be counted

before an external crystal clock can be considered as stable

and possible to select as the system clock.

•

EOCV = 128

It gives 1.63 ms delay for 40 MHz crystal oscillator

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