AN4266 datasheet(39/76 Pages) STMICROELECTRONICS

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AN4266

Functional safety requirements for application software

Doc ID 024283 Rev 2

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Figure 8.

Single Read Analog Input configuration

Hardware BIST

Three types of self-test algorithms have been implemented in the ADC hardware:

●

SUPPLY SELF-TEST

●

RESISTIVE-CAPACITIVE SELF-TEST

●

CAPACITIVE SELF-TEST

Hardware BIST implementationThe hardware BISTs shall be activated by the application in

one of the following modes:

●

CPU mode

●

CTU mode

In CPU mode, the application software takes care of the hardware self-test activation and

checks the test flow and the timing.

In CTU mode, the CTU module takes care of the hardware self-test activation, flow

monitoring, and timing. It is important to note that in this operating mode, the CPU does not

take part in running the hardware self-test.

HW self-tests use analog watchdogs to verify the outcome of self-test conversions. The

reference thresholds of these watchdogs are saved in test sector (See “Test flash memory”

section and “Test flash information” table in the SPC56xL70xx Reference Manual).

Mandatory: Before running the HW self-test, the customer must copy these thresholds from

the test sector into the watchdog registers (See “Self test analog watchdog” section of the

SPC56xL70xx Reference Manual).

ADC_x

Analog Single Read/Write Internal

Readback Configuration

AN[x]

Reference voltages

(Vdd_HV_ADRx and Vss_HV_ADR)

= Input Pad

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