RM0345 datasheet(25/38 Pages) STMICROELECTRONICS

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RM0345

Calibration software compatibility and configuration

Doc ID 024080 Rev 3

25/38

Table 14.

EBI_CAL_BRx register setting

bit

field

Name

Description

value

0-16

Base address

These bits are compared to the corresponding

unmasked address signals among ADDR[0:16] of the

internal address bus to determine if a memory bank

controlled by the memory controller is being accessed by

an internal bus master

Note: An MCU may have some of the upper bits of the

BA field tied to a fixed value internally in order to restrict

the address range of the EBI for that MCU. Refer to the

device-specific documentation to see which bits are tied

off, if any, for a particular MCU. Tied-off bits can be read

but not written. These bits are ignored by the EBI during

the chip-select address comparison. However, the

internal bridge of the MCU most likely requires that the

chipselect banks be located in memory regions

corresponding to the fixed values chosen

Port Size

The PS bit determines the data bus width of transactions

to this chip-select bank.

Note: In the case where the DBM bit in EBI_MCR is set

for 16-bit Data Bus Mode, the PS bit value is ignored and

is always treated as a ’1’ (16-bit port).

0b1

1 = 16-bit port

0 = 32-bit port

AD_MUX

Address on Data Bus

Multiplexing

The AD_MUX bit controls whether accesses for this chip

select have the address driven on the data bus in the

address phase of a cycle

0b1

1 = Address on Data Multiplexing Mode is enabled for

this chip select.

0 = Address on Data Multiplexing Mode is disabled for

this chip select.

WEBS

Write Enable / Byte

Select

This bit controls the functionality of the WE[0:3]/BE[0:3]

signals.

0b1

1 = The WE[0:3]/BE[0:3] signals function as BE[0:3]

0 = The WE[0:3]/BE[0:3] signals function as WE[0:3]

Burst Inhibit

This bit determines whether or not burst read accesses

are allowed for this chipselect bank. The BI bit is ignored

(treated as 1) for chip-select accesses with external TA

(SETA=1).

0b1

1 = Disable burst accesses for this bank. This is the

default value out of reset (or when SETA=1).

0 = Enable burst accesses for this bank]

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