TN0108

Peripherals

Doc ID 15874 Rev 2

11/26

5

Peripherals

5.1

Peripheral clock prescalers

On Cut 1.1 devices, the system clock divider enable bits DE0, DE1, and DE2 within the

system clock divider configuration registers are cleared out of reset. This means that any

attempt to access an off-platform peripheral without enabling the relevant clock divider will

result in a system crash.

On Cut 2 devices, the system clock divider enable bits are set out of reset to enable all the

peripheral clock prescalers.

Table 8.

System clock dividers

Silicon revision

DE0, DE1, DE2 in

GCM_SC_DC[0..2]

Implications

SPC560B Cut 1.1

Cleared out of reset

System clock to peripherals is disabled out of reset

SPC560B Cut 2

Set out of reset

System clock to peripherals is enabled out of reset