AN2115

Operation description

Doc ID 11165 Rev 5

13/33

Figure 9.

Equivalent circuit for voltage loop analysis

To complete the power stage analysis, the zero due to the output capacitor ESR should be

considered.

Equation 1

In Equation 1 the power stage transfer function is shown, where RO is the output equivalent

frequency based on the load value.

In order to have zero DC error regulation, the feedback voltage loop is implemented with an

integrator stage, the transfer function of which is shown in Equation 2.

Equation 2

Equation 3

placed at half of the switching frequency.

Once the gain loop is known, the system will be stabilized with the compensation network as

shown in the Section 6.1.4.

Hs

()

V

()

I

()

---------------

sC

1

+

()R

o

sC

R

o

+

() 1

+

----------------------------------------------------

=

=

Gs

()

g

A

V

-----------

sC

1

+

sC

C

-----------------------------

⎝⎠

⎛⎞

•

=

G

()

R

+

() sC

1

+

()

A

R

o

+

()

+

()

--------------------------------------------------------------------------------------------

=