Synchronization

AN2115

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Doc ID 11165 Rev 5

5

Synchronization

The device can also be synchronized with an external signal from 1 MHz up to 2 MHz

through the internal PLL. When the device is locked, the external signal and the high side

turn on rising edges are aligned. In this case, low noise mode is automatically selected.

The device could skip some cycles in very light load conditions depending on the

input/output conditions. The internal synchronization circuit is inhibited in short circuit and

overvoltage conditions in order to keep the protections effective (see relative sections).

can range typically from 20% to 80%. Occasionally, if the synchronization signal duty cycle

is very similar to the application duty factor, a jittering can be detected on the LX pin. In this

case some practical solutions are listed below:

1.

Change the synchronization signal duty factor.

2.

Decrease the synchronization signal amplitude.

3.

Add a 20 pF capacitor between the COMP pin and ground.

The device switches at 1.4 MHz (typ.) if no synchronization signal is applied.

5.1

Dropout operation

The Li-Ion battery voltage ranges from approximately 3 V to 4.2 V (depending on the anode

material). If the regulated output voltage is from 2.5 V and 3.3 V, it is possible for the battery

voltage to decrease to the regulated voltage near the end of battery life.

In this case, the device stops switching and works at 100% of duty cycle, minimizing the

dropout voltage and the device losses. The minimum input voltage necessary to ensure

output regulation can be calculated as:

Equation 8

resistance.

5.2

PGOOD (Power Good output)

a comparator with a threshold set at 90% of the reference voltage (0.6 V). Since the output

value. The internal comparator is triggered and the Power Good pin is pulled down. The pin

is an open drain output, so it should be connected to a pull up resistor. If the feature is not

required, the pin can be left floating.

5.3

Adjustable output voltage

The output voltage can be adjusted by an external resistor divider from a minimum value of

0.6 V up to the input voltage. The output voltage value is given by:

V

in

MIN

–

V

o

I

o

R

DS on

() HS

–

MAX

–

R

L

+

()

•

+

=