AN2478

Error detection features

7/21

3

Error detection features

This feature allows the output status detection to verify the functionality of the LEDs. The

error detection includes both open circuit detection and short circuit detection. From "normal

mode", the device is switched to "error mode" by a logic sequence on the OE/DM2 and

LE/DM1 pins. The eight data bits (STP08DP05) must be set to "1" in order to set all the

outputs ON during detection. The data are latched by LE/DM1. After latching, the outputs

are ready for the detection process. When the microcontroller switches the OE/DM2 to

"low", the device drives the LEDs in order to analyze if an open or short condition has

occurred.

In order to set the SDO output pin to the correct output error detection value, during the

acquisition time (OE/DM2 "low"), at least two CLK pulses must be applied before the rising

edge of OE/DM2 signal. These CLK pulses must be sent after the minimum detection time

(typically 500-600 ns). In this way the data loaded into the shift register will be updated

(rewritten) with the error detection data when the OE/DM2 signal turns to “high”. Good

output results are shown with a "1" logic level, and with a "0" logic level when the output is

malfunctioning (short or open condition).

The plots below show all the steps required to perform the error detection for the

STP08DP05 and the STP16DP05.

Figure 4.

Error detection sequence for STP08DP05

LE and OE

signal for Error

Detection Mode

Feeding 8 bit of CLK signal after entering

the EDM, the SDI signal, set to 1, is

loaded inside the shift register

This signal latches the

Data vs the SDO

Set the Enable “ON”, run 2

CLK cycle minimum, wait

1micro second minimum,

then apply other 1 CLK

cycle

Detection Results shown by SDO.

In this case all the outputs are

Open

After the Detection

Error Windows, an

OE Signal puts the

device in Normal

Mode