AN2808 datasheet(14/40 Pages) STMICROELECTRONICS

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Configuration

AN2808

14/40

7.2

JP1 DDR2/DDR3 or power-saving mode (DDRSEL pin)

The JP1 jumper provides different options depending on the configuration of JP3. If the fixed

output voltage is selected (JP3 in the lower position), the user can choose between 1.8 V

(DDR2) or 1.5 V (DDR3), connecting JP1 as shown in Figure 10, and the pulse-skip mode is

set by default.

When the adjustable output voltage is selected (JP3 in the upper position), the same jumper

allows choosing between forced pulse width modulation (PWM), pulse-skip and non-audible

pulse-skip modes.

7.3

JP2 output discharge (DSCG pin)

The JP2 jumper is used to select the desired output discharge when both the S3 and S5

signals are tied low. In the upper position the outputs are not discharged at all, while in the

lower position the outputs are independently discharged using the internal MOSFETs (22

Ω

for VDDQ and VTT, 1.5 k

Ω for VTTREF). When JP2 is in the central position, the tracking-

discharge is programmed. This discharge mode relies on the LDOIN pin being connected to

the VDDQ output. See Section 10.7: VDDQ, VTT and VTTREF turn-off (soft end). If an

external rail is used to supply the LDO, the tracking discharge cannot be used as the device

can be damaged while attempting to sink 1 A from the LDO input.

Figure 12.

JP2 (DSCG) setting

Figure 10.

JP1 options when JP3 is in

the lower position

Figure 11.

JP1 options when JP3 is in

the upper position

1.5V output voltage

1.8V output voltage

(default position)

1.5V output voltage

AM00647v1

No Audible Pulse-Skip

Forced PWM

(default position)

Pulse-Skip

AM00648v1

Non -Tracking Discharge

No Discharge

(default position)

AM00649v1

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