AN4650 datasheet(46/102 Pages) STMICROELECTRONICS

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Interrupt generation

AN4650

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DocID027415 Rev 1

used to set the Shock time window value: the default value of these bits is 00b and

corresponds to 4*ODR_XL time, where ODR_XL is the accelerometer output data rate. If

the SHOCK[1:0] bits are set to a different value, 1 LSB corresponds to 8*ODR_XL time.

In the double-tap case, the Quiet time window defines the time after the first tap recognition

in which there must not be any overthreshold. When the latch mode is disabled (LIR bit of

TAP_CFG is set to 0), the Quiet time also defines the length of the interrupt pulse (in both

single and double-tap case). The QUIET[1:0] bits of the INT_DUR2 register are used to set

the Quiet time window value: the default value of these bits is 00b and corresponds to

2*ODR_XL time, where ODR_XL is the accelerometer output data rate. If the QUIET[1:0]

bits are set to a different value, 1 LSB corresponds to 4*ODR_XL time.

In the double-tap case, the Duration time window defines the maximum time between two

consecutive detected taps. The Duration time period starts just after the completion of the

Quiet time of the first tap.The DUR[3:0] bits of the INT_DUR2 register are used to set the

Duration time window value: the default value of these bits is 0000b and corresponds to

16*ODR_XL time, where ODR_XL is the accelerometer output data rate. If the DUR[3:0] bits

are set to a different value, 1 LSB corresponds to 32*ODR_XL time.

Figure 16 illustrates a single-tap event (a) and a double-tap event (b). These interrupt

signals can be driven to the two interrupt pins by setting to 1 the INT1_SINGLE_TAP bit of

the MD1_CFG register or the INT2_SINGLE_TAP bit of the MD2_CFG register for the

single-tap case, and setting to 1 the INT1_DOUBLE_TAP bit of the MD1_CFG register or

the INT2_DOUBLE_TAP bit of the MD2_CFG register for the double-tap case.

No single/double tap interrupt is generated if the accelerometer is in Inactivity status (see

Section 4.6 for more details).

Figure 16. Single and double-tap recognition (LIR bit = 0)

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