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AN1228 데이터시트(PDF) 2 Page - STMicroelectronics

부품명 AN1228
상세설명  How to relate LMOS device parameters to RF performance
PDF  6 Pages
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AN1228 데이터시트(HTML) 2 Page - STMicroelectronics

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Breakdown voltage
AN1228
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1
Breakdown voltage
The saturated-drain-source breakdown voltage (BVDSS) of a MOSFET device is specified at
a particular value of current with the drain biased and the gate, as well as the source,
shorted. BVDSS can take many forms as represented in Figure 1 which shows the curve
tracer displays for LDMOS breakdown. A BVDSS curve can have a soft breakdown with
multiple breaks in the curve which is indicative of non-uniformities in the stress within the
inter-digitated cell structure.
Figure 1 shows a BVDSS curve with characteristics that are typical of a device exhibiting
punch-through due to an improper body-doping profile. There are four significant areas on
this curve - the low, mid, high and breakdown drain-voltage regions which reflect leakage,
punch-through, space-charge-limited current and avalanche current respectively. Figure 1
also shows a curve with a very sharp break where the current suddenly increases. There
are two significant regions on this curve - pre-breakdown and post-breakdown. Prior to
breakdown, leakage current exists that could be from many sources, such as the normal p-
type, n-type (pn) junction leakage due to recombination and generation of carriers in the
quasi-neutral region of the junction. The breakdown-voltage regime is the avalanching of
carriers due to the electric field being greater than the critical electric field (approximately
1x105 V/cm). Under these conditions an electron can be accelerated by the electric field.
Due to elastic and inelastic scattering this electron acceleration can generate more than one
carrier and thus a multiplication scheme transpires.
Figure 1.
Typical breakdown curves of a LDMOS transistor
Operating near BVDSS is a reliability risk since the device sustains high-stress conditions.
Under these conditions the high-energy carriers can alter the device characteristics by
creating, filling and emptying interface traps. For an LDMOS device, if this avalanche
condition exists under or near the gate, the hot carriers can penetrate the gate oxide as well
as alter the on- and off-state characteristics. Typical problems due to this avalanching
include threshold-voltage drift and increased gate leakage. While evaluating devices for this
parameter, large variations are indicative of inconsistencies in device fabrication. For RF
circuit design a general rule of thumb states that the BVDSS should be 2 to 2.5 times the
operating voltage in order to support variations in RF voltage.



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