AN1228 datasheet(3/6 Pages) STMICROELECTRONICS

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AN1228

Breakdown voltage

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The saturated gate-source current (IGSS) is the leakage current generated when the gate is

biased at a specified voltage while maintaining all other terminals at ground. IGSS leakage

is due to many factors that are related to the integrity of gate oxide and surrounding regions.

Ideally this value would be zero for voltage levels that are less than the voltage required to

reach the dielectric strength of the gate oxide. However, in practice this condition is not

achieved due to the omnipresence of impurities that exist in all wafer fabs and the vagaries

of the oxide growth with the temperature profiles used. IGSS can be used to evaluate the

reliability of this integral component of the MOSFET. An increase of this parameter with a

particular device stress can be used to extrapolate the mean time failure (MTTF) of the gate

oxide. Overstressing the gate either periodically with RF or statically with DC can also cause

an increase in this parameter and thus degrades device performance with respect to RF

power gain. Other considerations for the gate oxide include careful electrostatic-discharge

(ESD) precautions since the gate oxide is easily damaged.

IDSS is the current produced when the drain is biased at a specific voltage while maintaining

source and gate contacts at ground. IDSS has many component contributions. Normal pn

junction leakage is not a reliability problem as long as it is maintained at a specified value

and does not continue to increase indefinitely. Other sources of IDSS include minority carrier

injection from the source due to carriers overcoming the energy barrier resulting from

surface band bending and also from subcritical avalanching caused by high electric fields

due to a non-ideal body as well as the Laterally-Diffused-Drain (LDD) doping profile.

The reverse transfer capacitance Cgd is the feedback capacitance from the device drain to

the gate that limits MOS device high-frequency gain. This capacitance is a function of many

factors including the gate area, the gate-drain metallurgical overlap as well as the dynamics

of the drain-source depletion spread as a function of drain bias. The three regions of the

capacitance-voltage (CV) characteristics in Figure 2 are indicative of device formation.

Figure 2.

Reverse transfer capacitance vs. supply voltage

For LDMOS devices the zero-volt capacitance is mainly due to the gate-oxide capacitance

(Cox). The initial decrease in Cgd as bias is applied due to the formation of a depletion

capacitance, dictated by the doping profile that is in series with Cox. It is important that the

slope of this initial decrease is large and approaches its final value at some voltage near the

saturated drain-source voltage (VDS(sat)) due to linearity considerations. The gate-source

capacitance (Cgs) is the capacitance formed between the gate and the ground plane. The

LDMOS source, body, epitaxial layer and substrate form the referenced ground plane. The

charge formed by application of a voltage to the gate is dependent on the area of the gate,

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