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STR71x BSPI COMMUNICATION WITH M25P10-A SERIAL FLASH

3 M25P10-A SERIAL FLASH MEMORY MANAGEMENT AND CONFIGURATION

3.1 SUMMARY DESCRIPTION

The M25P10-A is a 1 Mbit (128k * 8) Serial Flash Memory, with advanced write protection

mechanisms, accessed by a high speed SPI-compatible bus. The memory can be pro-

grammed 1 to 256 bytes at a time, using the Page Program instruction.

The write protect pin (W) and the hold pin (H) are not used in our application (both are high

level).

3.2 STATUS REGISTER

The device has one status register which contains a number of control bits and status bits, as

shown in the following figure:

Figure 1. Status Register Control and Status Bits

The SRWD bit is operated in conjunction with the Write Protect (W) signal.

The BP1 and BP0 bits in the status register can be used to write protect a block of memory. In

this application, both bits are cleared, allowing write access to all memory.

The WEL bit indicates the status of the write enable latch.

The WIP bit indicates whether the memory is busy with a Write Status register, Program or

Erase cycle.

3.3 INSTRUCTION SET

Prior to any operation, the device must be selected (S pin at low level), then a one-byte

instruction code must be sent to the Serial Flash Memory. The device has a set of 11 instruc-

tions: (see Table 1, “Instruction Set,” on page 4).

00

0BP1

SRWD

BP0

WEL

WIP

Status Register Write Protect

Write Enable Latch Bit

Write in Progress Bit

Block Protect Bit