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Guidelines for connecting via JTAG protocol to the STR71x microcontroller

4.3 SWITCHING FROM DEBUG TO SYSTEM MODE

This section is not mandatory, but explains when the debugger needs to access the system

memory, this can be done by executing instructions temporarily in RUN mode.

– The ICE debug status register is read via scan chain2 to make sure we are still in debug

mode by checking DBGACK.

– Then switch back to scan chain1. In shifting data and the breakpoint bit into the scan chains,

the brkpt bit value is set to logic “0”

– Then the brkpt bit is set to logic "1" in order to execute an instruction at system speed re-

quested by the debugger, to return to system state ( to access system memory for example

that needs to be performed at system speed). This is done by performing RESTART to exit

debug state to execute the instruction at system speed (MCLK), then goes back to debug

state once the execution has ended (the core is then clocked with DCLK).

– The ICE debug status register is read to make sure the system has changed back to debug

mode by checking DBGACK.

– From which point we can execute instructions to the core in debug state using scan chain1.