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Guidelines for connecting via JTAG protocol to the STR71x microcontroller

2.4 CONNECTION SEQUENCE FROM STANDBY MODE

When the core is in Standby, the core and peripherals are powered down, therefore a straight

connection to the JTAG is not possible if the wakeup logic or system reset has not been trig-

gered. To exit Standby, the wakeup sequence needs to be run to switch the main voltage reg-

ulator (which supplies the core and on-chip peripherals) back on to its nominal value. The

wakeup procedure triggers a system reset sequence.

2.5 CONNECTION WHEN CODE IS EXECUTING FROM STR71x MEMORY

Attempting to connect while the STR71x is executing code from its memory is not recom-

mended as this is not considered as a robust solution. For example, the target could have al-

ready executed the code to put the STR71x in Standby mode and therefore any subsequent

attempt might fail.

3 CONNECTION METHODS

3.1 BOOT FROM FLASH, COPY TO RAM

One way to bypass the possibility of hitting a random instruction in RAM that might put the

system in an undefined state is to boot an application from address 0x0 in Flash which then

copies an image to internal RAM and executes from it. This will prevent any illegal or un-

wanted instruction being hit since the Flash is manufactured with known data contents, and

this is also the case when a flash sector is erased. This eliminates the possibility of hitting a

random code when the application is booted from internal RAM.

3.2 FLASH INITIALIZATION

As mentioned in Section 2, no JTAG connection to the target is possible during the Flash ini-

tialization phase, as described in Figure 2. The JTAG_EN signal is asserted and might reset

the ARM TAP.

Taking into account the Flash initialization procedure, the JTAG connection sequence can not

be initiated before phase 3 described in Figure 2.