UPD6462GS datasheet(29/60 Pages) NEC

29 / 60 page

µPD6461, 6462

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Control bits for the horizontal display start position

These bits are used to specify the horizontal display start position (timing) as one of 32 steps in units of 12 dots

(12/fOSC (MHz)). Settable positions are based on the rising edge of the horizontal synchronizing signal input to the

Hsync pin. The 32 positions are calculated by adding 12 dots, one to 32 times, to the position equivalent to 16 clock

pulses (16/fOSC (MHz)) from the rising edge (fOSC (MHz): LC oscillation frequency or external input clock frequency).

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Control bits for the vertical display start position

These bits are used to specify the vertical display start position as one of 32 steps in units of three lines (or 32

steps in units of nine lines when specified with a mask option). The minimum settable position is three lines from a

rising edge of the vertical synchronizing signal input to the Vsync pin.

Horizontal synchronizing signal (Hsync)

Display area of 12 rows x 24 columns

Vertical synchronizing signal (Vsync)

A : 3H

×(24V4+23V3+22V2+21V1+20V0)+1H

9H when units of nine lines are selected by specifying a mask option

B :

 ×(24H4+23H3+22H2+21H1+20H0+1) + 

fOSC(MHz)

fOSC : LC oscillation frequency or external input clock frequency

H : Line

UPD6462GS 데이터시트(PDF) 29 Page - NEC