UPD6462GS datasheet(53/60 Pages) NEC

53 / 60 page

µPD6461, 6462

CHARACTER AND BLK SIGNAL OUTPUT

Character and BLK signals are output in synchronization with the falling edges of the dot clock.

CDL

DTW

CUS

CDS

50 %

90 %

10 %

Dot clock

Character signal

BLK signal

OUTPUT TIMINGS (TA = –20 to +75˚C, pins: VR, VG, VB, VBLK, VC1, BLK1, VC2, BLK2, (RBLK, GBLK, BBLK))

Pins in parentheses are selected by specifying a mask option.

Note

Min.: (1/fOSC) – 5 ns, Max.: (1/fOSC) + 5 ns

fOSC: Frequency of LC oscillation or external input clock.

TIMING FOR CONTINUOUS COMMAND INPUT

When inputting commands continuously, the following timing requirements must be observed:

(TA = –20 to +75˚C, VDD = 2.7 to 5.5 V)

fOSC: Frequency of LC oscillation or external input clock (MHz), S: Character size (single (minimum) or double), tHWL: Hsync width.

Commands other than VRAM write commands may not comply with T2 provided the control clock cycle satisfies the specifications.

Hi-Z

DATA

CLK

Hi-Z

Parameter

Continuous command input timing 1

Continuous command input timing 2

Conditions

For all commands

For VRAM write

commands

Min.

2.0

µs + (21/fOSC)

× S +tHWL

µs + (12/fOSC)

× S

Typ.

Max.

Unit

µs

Symbol

When display is

turned on

When display is

turned off

Parameter

Output delay of character/BLK signal

Rise time of character/BLK signal

Fall time of character/BLK signal

Time equivalent to minimum dot

Conditions

VDD = 4.5 to 5.5 V, output load capacity = 10 pF

VDD = 2.7 to 3.3 V, output load capacity = 10 pF

VDD = 4.5 to 5.5 V, output load capacity = 10 pF

VDD = 2.7 to 3.3 V, output load capacity = 10 pF

VDD = 4.5 to 5.5 V, output load capacity = 10 pF

VDD = 2.7 to 3.3 V, output load capacity = 10 pF

VDD = 4.5 to 5.5 V, output load capacity = 10 pF

VDD = 2.7 to 3.3 V, output load capacity = 10 pF

Min.

Typ.

Max.

Unit

Symbol

CDL

CUS

CDS

DTW

(1 /Oscillation

frequency)

±5Note

(1 /Oscillation

frequency)

±5Note

UPD6462GS 데이터시트(PDF) 53 Page - NEC

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