전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

UPD64AMC 데이터시트(PDF) 12 Page - NEC

부품명 UPD64AMC
상세설명  4-BIT SINGLE-CHIP MICROCONTROLLER FOR INFRARED REMOTE CONTROL TRANSMISSION
PDF  64 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  NEC [NEC]
홈페이지  http://www.nec.com/
Logo NEC - NEC

UPD64AMC 데이터시트(HTML) 12 Page - NEC

Back Button UPD64AMC Datasheet HTML 8Page - NEC UPD64AMC Datasheet HTML 9Page - NEC UPD64AMC Datasheet HTML 10Page - NEC UPD64AMC Datasheet HTML 11Page - NEC UPD64AMC Datasheet HTML 12Page - NEC UPD64AMC Datasheet HTML 13Page - NEC UPD64AMC Datasheet HTML 14Page - NEC UPD64AMC Datasheet HTML 15Page - NEC UPD64AMC Datasheet HTML 16Page - NEC Next Button
Zoom Inzoom in Zoom Outzoom out
 12 / 64 page
background image
12
µPD64A, 65
Data Sheet U14380EJ2V0DS00
2.8 Arithmetic and Logic Unit (ALU): 4 Bits
The arithmetic and logic unit (ALU), which refers to an arithmetic circuit consisting of 4 bits, executes simple
manipulations with priority given to logical operations.
2.9 Flags
2.9.1 Status flag (F)
Pin and timer statuses can be checked by executing the STTS instruction to check the status flag.
The status flag is set (to 1) in the following cases.
• If the condition specified with the operand is met when the STTS instruction has been executed
• When STANDBY mode is released.
• When the release condition is met at the point of executing the HALT instruction.
(In this case, the system
is not placed in STANDBY mode.)
Conversely, the status flag is cleared (to 0) in the following cases:
• If the condition specified with the operand is not met when the STTS instruction has been executed.
• When the status flag has been set (to 1), the HALT instruction executed, but the release condition is not met
at the point of executing the HALT instruction. (In this case, the system is not placed in STANDBY mode.)
Table 2-1. Conditions for Status Flag (F) To Be Set by STTS Instruction
Operand Value of STTS Instruction
Condition for Status Flag (F) To Be Set
b3
b2
b1
b0
0000
High level is input to at least one of KI pins.
0
1
1
High level is input to at least one of KI pins.
1
1
0
High level is input to at least one of KI pins.
1
0
1
The down counter of the timer is 0.
1
Either of the combinations
[The following condition is added in addition to the above.]
of b2, b1, and b0 above.
High level is input to at least one of S0, S1, and S2Note pins.
Note The use of STOP mode release for the S2 pin must be enabled (bit 3 of P4 register is set to 1.)



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com