AN2797

DDR memory interface

Doc ID 14841 Rev 1

13/23

or planes. Do not place a decoupling capacitor at the junction of the resistors - only at the

Vref balls. If the Vref trace length must be long, the divider resistor value should be close to

2x the characteristic impedance of the Vref trace; 150 ohms should work well without

consuming too much power. If a long trace and/or noise coupling results between the DRAM

and controller, then it is preferable to generate a separate Vref for the DRAM and controller.

2.8

Observability

It is important to be able to observe important signals for system validation, timing, signal

quality, and debugging. Place test points on any signals or set of signals that may be needed

for these purposes. Always provide a ground via nearby any test points (<4mm) for the

probe ground. Only very small test point pads can be used, preferably just a signal via. Or if

there is insufficient space, simply a window in the solder mask over a trace can serve the

purpose. Do not create test point structures that may significantly degrade signal quality, for

example, large test points, stubs, etc.

Test points should be located at both ends of the trace (two test points per signal), as close

to the device balls as practical (a via next to the ball is preferable, untented on the bottom). It

is especially important to be able to observe signals at both the driving and receiving ends

of a trace in high-speed interfaces to validate timing parameters, and quantify driver

behavior and reflections. Observing a signal at only one end may hide important features

that are evident at the other end, even with very short traces as is the case in a point-to-

point DDR interface.

In a DDR memory interface the routing and component density is too high to add test points

on all signals. A subset of DDR signals with test points is a good compromise. Test points for

the following DDR signals should be included in all designs:

●

CLK/nCLK

●

DQS/nDQS (all data lanes)

●

DQ (Select a small number of signals that are representative of best and worst signal

paths, at least two DQ signals.)

●

Address and Command (Select subset of signals that are of interest and that are

representative of best and worst signal paths.)