AN2797

Low-inductance decoupling capacitor layout

Doc ID 14841 Rev 1

21/23

A.2

Low inductance layout for decoupling capacitors

Figure 10 shows a low inductance layout for a 0402 decoupling capacitor using 2 vias with a

10 mil drill size. The main features are

1.

Vias placed close to the lands

2.

Vias of opposite polarity place close together

3.

Trace connecting land to via is wide.

Figure 10.

Low-inductance layout for 0402 package.

Table 7.

Dimensions for compact 0402 land pattern

Dimension

Value

Units

A20

mils

B20

mils

C15

mils

Table 8.

Dimensions for a low inductance capacitor layout

Dimension

Value

Units

D (land to hole)

1.

The land to hole separation is determined by the PCB fabrication tolerances. This is usually 8 - 10 mils.

mils

E (hole to hole)

2.

This distance should be minimized, consistent with PCB fabrication tolerances, typically about 30 mils. If

the capacitor is placed within a BGA ball field, dimension E should be the same as the ball pitch

mils

F (trace width)

20

mils