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UPD703003GC 데이터시트(PDF) 27 Page - NEC |
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UPD703003GC 데이터시트(HTML) 27 Page - NEC |
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27 / 82 page ![]() 27 µPD703003 Data Sheet U12261EJ2V1DS00 The configuration of the clock-synchronized serial interfaces 0 to 3 (CSI0 to CSI3) is shown below. Figure 9-2. Block Diagram of Clock-synchronized Serial Interfaces 0 to 3 (CSI0 to CSI3) Note SO0 to SO2, SCK0 to SCK2: CMOS outputs SO3, SCK3: N-ch open-drain outputs Remark n = 0 to 3 φ : internal system clock Internal bus CTXEn CRXEn CSOTn MODn CLSn1 CLSn0 CSIMn SIn SOn SCKn Shift register (SIOn) SO latch DQ 2 1 Serial clock control circuit Serial clock counter Interrupt control circuit INTCSIn Baud rate generator /2 Note Note φ φ |
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