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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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UPD703003GC 데이터시트(PDF) 21 Page - NEC |
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UPD703003GC 데이터시트(HTML) 21 Page - NEC |
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21 / 82 page  21 µPD703003 Data Sheet U12261EJ2V1DS00 7. CLOCK GENERATION FUNCTIONS The features of the clock generation functions are shown below. • Multiplier function using PLL clock synthesizer • Clock sources • Oscillation via resonator connection (PLL mode): fXX = φ, 2 × φ, φ/5 • External clock (PLL mode): fXX = φ, 2 × φ, φ/5 • External clock (direct mode): fXX = 2 × φ • Power saving control • HALT mode • IDLE mode • Software STOP mode • Clock output inhibit mode The configuration of the clock generation functions is shown below. Figure 7-1. Block Diagram of Clock Generation Functions X1 X2 CKSEL (fXX) CLKOUT CPU, On-chip peripheral I/O Clock generator φ Remark φ : internal system clock |
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