AN3100

Pad descriptions and configurations

Doc ID 16606 Rev 2

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Pad descriptions and configurations

To ensure correct behavior of the memory controller in any application, you need to properly

configure the various pads that interface the DDR memory.

The following table contains the complete list of the SPEAr3xx pads involved with the use of

DDR.

.

Table 4.

SPEAr3xx memory controller pads

Signal

Pad type

Direction

DDR_MEM_COMP2V5_REXT ANADDRGNDCORE_1V8_2V5_SF_TF_2ROWS

DDR_MEM_GNDBGCOMP

ANADDRGNDCORE_1V8_2V5_SF_TF_2ROWS

DDR_MEM_ADDR[14:0]

BDPROGDDRSCARUDQP_VDDE_1V8_2V5_SF_TF_2ROWS

BDPROGDDRSCARUDQP_GNDE_1V8_2V5_SF_TF_2ROWS

OUT

DDR_MEM_RAS

BDPROGDDRSCARUDQP_VDDE_1V8_2V5_SF_TF_2ROWS

OUT

DDR_MEM_CAS

BDPROGDDRSCARUDQP_GNDE_1V8_2V5_SF_TF_2ROWS

OUT

DDR_MEM_WE

BDPROGDDRSCARUDQP_VDDE_1V8_2V5_SF_TF_2ROWS

OUT

DDR_MEM_CS[1:0]

BDPROGDDRSCARUDQP_VDDE_1V8_2V5_SF_TF_2ROWS

BDPROGDDRSCARUDQP_GNDE_1V8_2V5_SF_TF_2ROWS

OUT

DDR_MEM_BA[2:0]

BDPROGDDRSCARUDQP_VDDE_1V8_2V5_SF_TF_2ROWS

BDPROGDDRSCARUDQP_GNDE_1V8_2V5_SF_TF_2ROWS

OUT

DDR_MEM_CLKEN

BDPROGRESDDRSCARUDQP_GNDE_1V8_2V5_SF_TF_2ROWS

OUT

DDR_MEM_GATE_OPEN[1:0]

BDPROGDDRSCARUDQP_VDDE_1V8_2V5_SF_TF_2ROWS

BDPROGDDRSCARUDQP_GNDE_1V8_2V5_SF_TF_2ROWS

INOUT

DDR_MEM_ODT[1:0]

BDPROGDDRSCARUDQP_VDDE_1V8_2V5_SF_TF_2ROWS

BDPROGDDRSCARUDQP_GNDE_1V8_2V5_SF_TF_2ROWS

OUT

DDR_MEM_DM[1:0]

BDPROGDDRSCARUDQP_VDDE_1V8_2V5_SF_TF_2ROWS

BDPROGDDRSCARUDQP_GNDE_1V8_2V5_SF_TF_2ROWS

OUT

DDR_MEM_DQS[1:0]

BDCLKDDRSCARUDQP_1V8_2V5_SF_TF_2ROWS

INOUT

nDDR_MEM_DQS[1:0]

BDCLKRESDDRSCARUDQP_INPUT_DQS_1V8_2V5_SF_TF_2ROW

S

INOUT

DDR_MEM_DQ[15:0]

BDPROGDDRSCARUDQP_VDDE_1V8_2V5_SF_TF_2ROWS

BDPROGDDRSCARUDQP_GNDE_1V8_2V5_SF_TF_2ROWS

INOUT

DDR_MEM_CLKP

BDCLKRESDDRSCARUDQP_INPUT_DQS_1V8_2V5_SF_TF_2ROW

S

OUT

DDR_MEM_CLKN

BDCLKRESDDRSCARUDQP_INPUT_DQS_1V8_2V5_SF_TF_2ROW

S

OUT

DDR_MEM_VREF

VREFSSTL_1V8_2V5_SF_TF_2ROWS

DDR2_EN

BDPROGSTARUDQP_1V8_2V5_3V3_TF3V3_2ROWS

IN