AN3100

Pad descriptions and configurations

Doc ID 16606 Rev 2

19/24

Figure 5.

Clock cell

All the pins of the digital cells are controlled on the basis of the configuration of the

miscellaneous register DDR_PAD register (0xFCA800F0). Refer to the corresponding

SPEAr3xx user manual for further details.

EN

TEN

TM

A

TA

Output part

ENZI

ZI

ODTA

ODTEN

ODTB

On-die

300

Ω

300

Ω

300

Ω

300

Ω

MODEZI2V5

DDR2V5

SEP

SEN

Input part

On-die

300

Ω

300

Ω

300

Ω

300

Ω

terminations

terminations

PU2V5

PU2V5

PDN2V5

PDN2V5

Pull-up and

pull-down

Pull-up and

pull-down

50 k

Ω

50 k

Ω

50 k

Ω

50 k

Ω

VDDE

VDDE

VDDE

VDDE

VDDE VDDE

VDDEPAD

GNDEPAD

BOOST

TRIGGER

VDD VDDE

GNDE

GND

A[0:6]SRC

PROGA2V5

ZOUTPROGA2V5