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AN3209 데이터시트(PDF) 16 Page - STMicroelectronics |
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AN3209 데이터시트(HTML) 16 Page - STMicroelectronics |
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16 / 42 page ![]() Component overview AN3209 16/42 Doc ID 17419 Rev 2 Figure 11. STM8L101K3 functional block diagram 2.2.2 STM8L101K3 I2C interface The STM8L101K3 I2C peripheral allows multimaster and slave communications with bus error management in standard (up to 100 kHz) or fast (up to 400 kHz) mode. In the demonstration datalogger application, only the single master mode is used. I2C synchronous communications require only two signals: SCL (Serial clock line) and SDA (Serial data line). The corresponding port pins must be configured as floating inputs. Refer to the STM8L101K3 datasheet for additional details. To manage errors resulting from I2C and RF arbitration, an error management mode has been implemented in the I2C library, i2c_ee.c, called by the M24LR64- R_Datalogger_application_firmware (see AN3057 for details). |
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