Memory organization

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Memory organization

This section describes the memory organization corresponding to:

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Access line and performance line STM8S microcontrollers

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Medium and high density STM8A microcontrollers

STM8S microcontrollers offer low density (8 Kbytes), medium density (from 16 to

32 Kbytes) and high density (from 32 to 128 Kbytes) Flash program memory, plus data

EEPROM.

STM8A microcontrollers feature medium density (from 8 to 32 Kbytes) and high density

(from 32 to 128 Kbytes) Flash memory, plus data EEPROM.

The memory organization differs from one STM8 family to another. Refer to Section 2.1,

Section 2.2, Section 2.3, Section 2.4, and Section 2.3 for a description of the memory

organization according to microcontroller family and memory density.

A memory accelerator takes advantage of the parallel 4-byte storage, which corresponds to

a word. The Flash program memory and data EEPROM can be erased and programmed at

byte level, word level or block level. In word programming mode, 4 bytes can be

programmed/erased during the same cycle, while in block programming mode, a whole

block is programmed/erase during the same cycle. Refer to Section 2.1, Section 2.2,

Section 2.3, Section 2.4, and Section 2.3 for information on block size according to the

devices.

2.1

Low density STM8S microcontrollers

The memory array is divided into two areas:

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8 Kbytes of Flash program memory organized in 128 pages or blocks of 64 bytes each.

The Flash program memory is divided into 2 areas, the user boot code area (UBC),

which size can be configured by option byte, and the main program memory area. The

Flash program memory is mapped in the upper part of the STM8S addressing space

and includes the reset and interrupt vectors.

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640 bytes of data EEPROM (DATA) organized in 10 pages or blocks of 64 bytes each.

One block (64 bytes) contains the option bytes of which 11 are used to configure the

device hardware features. The options bytes can be programmed in user, IAP and

ICP/SWIM modes.

Refer to Table 1 for a detailed description of the memory partition for low density STM8S

microcontrollers.